For convolutional coding, transmitted digital data symbols are provided with redundancy so that error detection and error correction is made possible at the receive end.
FIG. 1 shows a 64-QAM transmitter as taught in the prior art. The data originating from a data source DQ are coded in a Reed-Solomon coder and interleaved and transmitted, after scrambling in a scrambler V, to a serial/parallel converter S/P that converts the received scrambled serial data stream into six parallel data streams. In a 64-QAM transmitter, 28 bits of the serial data stream are converted, in accordance with the ITUJ.83 data standard for DOCSIS cable modems, by the serial/parallel converter S/P into four data streams of five bits that are transmitted directly via the data lines d1-d4 in uncoded form, to a downstream QAM mapper. Four bits of the received 28 bits are respectively applied to a coder via data bit lines d5, d6. After coding in a differential precoder (DPC), the four precoded data bits are fed to a binary convolutional coder CCI, CCII (CC=Convolutional Coding).
The convolutional coders CI, CI each have a puncturing circuit PI, PII connected downstream of them. According to the ITUJ.83 standard, in each case convolutional coders CCI, CCII with a code rate r=½ are used, the applied differentially precoded four data bits in the convolutional coder being recoded into eight data bits, five data bits of which are transmitted to the QAM mapper via the data lines d7, d8 by means of the puncturing circuit P. The QAM mapper performs the quadrature-amplitude-modulated output signal, which can assume 64 statuses, from the six parallel data streams applied, and transmits the output signal to a QAM receiver via a transmission channel K.
FIG. 2 shows a 64-QAM transmit signal with in-phase component I and quadrature component Q.
FIG. 3 shows the structure of a convolutional coder CC. The convolutional coder CC has an input E and an output A. The serial data stream applied to the input E is written into a k-bit-wide first stage. For each input bit, n output bits are generated. These bits are linear combinations of the data bits contained in the shift register. The convolutional coder CC shown in FIG. 3 has M stages that each contain k data bits. The input bits are composed of a block of k data bits that are written into the first stage 1. The data bits of a stage are shifted to the next stage. The data bits of the last stage are extracted or deleted. The code rate r of the convolutional coder CC is k/n.
As in the case of the block codes, redundancy is additionally added during the convolutional coding in order to be able to detect and correct errors. An essential difference between block codes and convolutional coders is that individual data blocks cannot be successively coded in the latter, but rather continuous coding takes place. The current coding of a transmit data sequence depends on the preceding transmit data sequences.
In each case k new transmit data bits are written into the first stage of the convolutional coder per clock cycle. The number M of stages (constrained length) indicates the number of clock cycles of k new data bits over which a written-in data bit influences the code word. The contents of the individual registers are read out by means of logic-operation circuits and added in v modulus 2 adders and subsequently sampled. The type of logic operations comprises the actual coding rule of the convolutional coder CC.
The method of operation of a convolutional coder CC according to the prior art as represented in FIG. 3 will be explained below by means of an example.
The convolutional coder CC illustrated in FIG. 4 has three stages each with a data bit and a coding rate of ½(M=3, k=1, r=½).
The applied transmit data sequence D(x)=(101) is recoded by the convolutional coder CC into the coded output signal sequence C(x)=(1110001011).
In polynomial representation, the convolutional coder illustrated in FIG. 4 can be described as:G1(x)=1+x+x2 G2(x)=1+x2C(x)=D(x)G1(x) interleaved with D(x)G2(x).
FIG. 5 shows a status diagram of the convolutional coder illustrated in FIG. 4. The M−1 states of the right-hand part of the shift register composed of three bits are represented in the rectangles. Either the crossovers of the dashed or of the continuous diagram lines are passed through depending on the data bit written in per clock cycle.
If the written-in data bit is a logic zero, the crossovers that are illustrated as a continuous line will take place, whereas when a logic one is written in the crossovers represented by broken lines take place.
FIG. 6 shows the associated tree diagram of the convolutional coder CC represented in FIG. 4. The longer the sequence of data to be transmitted, the more confusing the representation as a tree diagram.
The convolutional rule of a convolutional coder CC is therefore represented in a clearer way than what is referred to as a trellis diagram. FIG. 7 shows the trellis diagram of the convolutional coder CC illustrated in FIG. 4. The four lines correspond to the states of the right-hand part of the register of the convolutional coder. For each clock there are 2 k branching points. As in the status diagram illustrated in FIG. 5, when there is a logic zero as input bit the crossover represented as a continuous line takes place, whereas when a logic one is written in the crossover represented as a broken line takes place. The pairs of numbers associated with the lines each indicate the output values of this status crossover. After M clocks, in each case 2 k different branchings converge again.
FIGS. 8a-8h show by way of example the method of operation of a Viterbi decoder for the coding of a convolutionally coded reception signal as used in receivers according to the prior art. In the example illustrated in FIG. 8a, the Viterbi decoder decodes a convolutionally coded reception signal that has been coded by the convolutional coder CC that is illustrated in FIG. 4 and has the trellis diagram illustrated in FIG. 7. The transmitted code sequence is Cs(x)=(1101010001) in the example illustrated in FIG. 8.
The code sequence received by the receiver (with errors) is: CE(x)=(1101011001).
As in the first step illustrated in FIG. 8a, the first two digits of the received code sequence (11) are compared with the output values of the two trellis branchings. The calculation of the Hamming distance as a metric value yields the value 2 for the upper branching and the value 0 for the lower branching. At the next clock, the Hamming distance between the next digits of the received code sequence (01) and the output values of the now four branchings of the trellis diagram is calculated. FIG. 8b shows the accumulated metric values that are obtained from the sum of the previous metric value of the path and of the metric value calculated for this step.
The calculation of the metric values for the next two digits is carried out in an analogous fashion. FIG. 8c shows the calculated result. As can be seen in FIG. 8c, an end point of in each case two paths now is reached. This is generally the case after M clock pulses. Of these further clock pulses, only that with the lower accumulated metric is used by these two paths for the further calculation. As a result, a significant reduction in the necessary storage requirement in the Viterbi decoder is possible. FIG. 8c shows the result of this selection.
The following two clocks and the respective selection are illustrated in FIGS. 8e-8h. The path printed in bold in FIG. 8h represents, for the overall metric one, the path with the lowest metric.
A comparison of this discovered path with the trellis diagram illustrated in FIG. 7 shows that this signal path corresponds to the code sequence (111010001), i.e. to the code sequence Cs(x) that is actually transmitted. The transmit error was implicitly corrected by means of the Viterbi decoder. This error correction took place in the fourth clock pulse (see FIGS. 8e and 8f) in the example shown. The fact that an error was corrected by the Viterbi decoder is apparent from the fact that the overall metric is no longer equal to zero, as was still the case at the third clock pulse, but rather equal to one. By means of the metric value m, an estimate of the error rate is therefore obtained. By means of the calculated metric value, it is thus possible to estimate the connection quality of the transmission channel. If the case occurs that two different paths of an end point yield the same overall metric, it is possible to detect from this that more errors have occurred than can be corrected. The method of operation of a Viterbi decoder is described in IEEE, Vol. 61, No. 3, March 1973 “The Viterbi Algorithm”.
FIG. 9 shows a QAM receiver according to the prior art. The convolutionally coded transmit signal that is output by the 64-QAM transmitter illustrated in FIG. 1 via the transmission channel K is demodulated in an equalizer and the in-phase component I and the quadrature component Q of the QAM transmit signal represented in FIG. 2 are fed to a switching device S. The received data symbols are applied to the input of a Viterbi decoder by the equalizer EQ via the switched data lines. The Viterbi decoder decodes the applied convolutionally coded reception signal and in the process the reception signal sequence is continuously compared with theoretically possible transmit signal sequences, and the degree of correspondence is made the basis of the decision using a static estimation method. The higher value data bits that are output by the Viterbi decoder are fed directly to a parallel/serial converter P/S via four data lines, while the low value data bits are firstly decoded in a differential decoder and then fed to the parallel/serial converter PS. The decoded data is passed on from the output of the parallel/serial converter P/S to any desired data sink DS for further data processing.
In the 64-QAM transmitter illustrated in FIG. 1, the convolutional coders CC each code bit groups composed of four bits that are applied to the data lines d5, d6 in bit groups composed of five bits that are output to the QAM mapper via data lines d7, d8. By puncturing the data bit stream that is output by the convolutional coder CC, three QAM data symbols are generated by the QAM mapper based on the first three data bits, while two further QAM data symbols are generated based on the last of the four input data bits. Puncturing at the puncturing circuit P ensures that a data sequence that follows in accordance with the standard ITUJ.83 is output to the QAM mapper by the coder via the data lines d7, d8:C(x)=x0, x0, x0, x1, x0.
The QAM mapper thus generates three QAM transmit data symbols by means of three iterations or shift operations of the two convolutional coders. Two QAM symbols are then generated by means of an iteration or a shift operation of the two convolutional coders.
A synchronization operation must therefore take place in the 64-QAM receiver, as illustrated in FIG. 9, because the three QAM data symbols are to be processed by the Viterbi decoder in a way that differs from that for the next two QAM data symbols.
Therefore, the 64-QAM receiver illustrated in FIG. 9 according to the prior art contains a synchronization circuit. The synchronization circuit is connected to the output of the parallel/serial converter P/S. The data sequence that is output by the parallel/serial converter P/S in the synchronization circuit is compared with a stored known synchronization word data pattern until the synchronization circuit detects correspondence. In the process, a plurality of received data frames are sampled until at least two data frames at the correct data interval contain the known synchronization data word.
However, such a conventional synchronization operation has a number of disadvantages. The synchronization circuit, as illustrated in FIG. 9, requires a comparator memory for the various synchronization data words FSYNC that differ in a 256-QAM receiver and a 64-QAM receiver. In addition, two different search algorithms must be implemented for sensing the different training sequences. A separate counter is provided for sensing the distance between the transmitted data frames. The distance is different in E4-QAM signals and 256-QAM signals. A further counter counts the number of sensed frames. A further counter must be provided for checking for the resetting operation. Because the transmitted synchronization words are approximately 2 milliseconds apart from one another, the time for the synchronization operation in the conventional 64-QAM receiver illustrated in FIG. 9 is long.